1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices and, more particularly, to a method of selectively forming silicide film of merged DRAM and LOGIC (MDL) having a dual gate.
2. Description of the Related Art
As the degree of integration of semiconductor devices increases, a combined chip (for example, MDL) in which memory cells (DRAM cells) and logic circuits are merged into a chip has been created in compliance with a user""s various requirements as a preliminary step in forming a system on a chip. Since the combined chip of MDL is fabricated in such a manner that separate memories and logic are integrated in one chip, it has merits such as miniaturization, lower waste of electric power, higher speed, and realization of electromagnetic interference noise (EMI). Accordingly, many attempts to study and develop it have actively been made in many fields.
In the fabrication of MDL, the silicide film is formed throughout the whole region of a semiconductor device (for example, gate electrode and active regions in which DRAM cells are formed and a logic circuit region in which logic circuits are formed) in order to lower the resistance of the active region, gate electrode, and contact, thereby increasing operation capability in terms of device current and decreasing dependence of device characteristics on contact layout. Such a fabrication method is intended to prevent signal delays due to RC time constants, power consumption increase and degradation in high-speed operation, all of which can be caused by increases in contact and sheet resistance due to the reduction in the line width of gate electrodes and contact size as the degree of integration of the MDL chip is increased.
However, in the event that the silicide film is formed throughout the whole region of a semiconductor device, the junction leakage in a memory cell region (particularly, in an active region in which the storage node of cell capacity is formed) increases due to the silicide film formed in the active region of DRAM forming region, thereby decreasing the capability in data storage and lowering the refresh characteristic of the DRAM cell.
In order to solve such a problem, there was recently suggested a method by which the silicide film is selectively formed in a gate electrode region and an active source region of the logic circuit forming region (source and drain regions) only. Under this approach, the silicide film is not formed in the DRAM forming region.
There are various methods for selectively forming a silicide film in a specific region only. The most commonly used method includes formation of a silicide blocking layer (hereinafter, referred to as SBL) in a region other than the region in which a silicide film is formed. A silicide film is selectively formed in the region that does not include the SBL using a photolithography process of critical level. However, this method causes various difficulties such as reduced process margins in both the SBL and silicide film caused by misalignment in the etching process. As a result, there is an increasing trend to fabricate the MDL is utilizing a new selective silicidation process which results in improvement over the conventional method.
FIGS. 1a to 1d illustrate this method, i.e., the sequential steps for selectively forming the silicide film of an MDL having a dual gate. In the drawings, reference xe2x80x9cAxe2x80x9d indicates a DRAM forming region and xe2x80x9cBxe2x80x9d indicates a logic forming region.
Referring to FIG. 1a, in a first step, an undoped polysilicon film is deposited on a semiconductor substrate (silicon) 10 that is formed with shallow trench isolation (STI) 12. The polysilicon film is doped with a low concentration of impurity by ion-implanting a low concentration of impurity into the film to the degree that the DRAM cell transistor can operate. Next, the polysilicon film is selectively etched utilizing a mask of a resist pattern that limits the gate electrode-forming region so that a gate 14 is formed on each of the DRAM cell forming region A and logic circuit forming region B. Then, the lightly doped drain (LDD) region (not shown) is formed on the substrate 10 within both edge sides of the gate. Subsequently, an insulating spacer 16 is formed on each of the sidewalls of the gate 14. Thereafter, the resist pattern is formed in the DRAM forming region A so that the logic-forming region B is opened. With the resist pattern as a mask, a high concentration of N type impurity (N+ type) is ion-implanted into the NMOS transistor forming region on the resultant material and a high concentration of P type impurity (P+ type) is ion-implanted into the PMOS transistor forming region. The resist pattern is then removed. As a result, in the logic circuit forming region B, the NMOS forming region is formed thereon with the N+ type gate and the N+ type source/drain regions having a LDD structure, and the PMOS forming region is formed thereon with the P+ type gate and the P+ type source/drain regions having a LDD structure.
As shown in FIG. 1b, a nitride film 18 for SBL is formed on the substrate 10 that is formed therein with the gate 14 and the spacer 16, and the oxide film 20 for SBL of USG material is formed on the nitride film 18 to a thickness of approximately 2500 xc3x85 with reference to the upper surface of the gate 14. Thereafter, the oxide film 20 is dry-etched using a blanket etch-back process. At this time, the oxide film is dry-etched to a thickness of approximately 3100 xc3x85 with reference to the active region on the substrate. As a result, in the DRAM cell forming region A in which the gap between the gates is very narrow, the oxide 20 remains at a thickness as much as the active region is sufficiently filled. In the logic circuit forming region B in which the gap between the gates 14 is broad, the oxide 20 remains at a thickness less than in the DRAM forming region A side. The reason that a part of the oxide film 20 for SBL is first dry-etched is to reduce the time that takes in etching the oxide film 20 in a following wet-etch back process.
As shown in FIG. 1c, the oxide film 20 is etched back by a wet-etching method so that the nitride film 18 for SBL on the gate 14 may be exposed. Thereby, the oxide film 20 for SBL remains with a thickness of several hundred xc3x85 by self-alignment just in the active region of the DRAM cell forming region A where the space between the gates is narrow.
The reason that the oxide film 20 remains in only the active region of the DRAM cell forming region A is that, since the active region (source/drain regions) of the logic circuit forming region B is wider in its size than the active region of the DRAM cell forming region A, the oxide film 20 in the logic circuit forming region B is entirely removed. In contrast, the oxide film 20 in the DRAM cell forming region A is not entirely removed.
As shown in FIG. 1d, the nitride film 18 for SBL in the other region excluding the region in which the oxide film 20 remains is dry-etched, thereby exposing the silicide film forming region (for example, the gate surface of the DRAM cell forming region, the gate surface of the logic circuit forming region, and the surface of the active region). Refractory metals such as Co, Ti, Ni are deposited on the resultant material and are heat treated. At this time, the silicon and the refractory metals react and the silicide film 22 of low resistance is formed in the oxide film-removed region. In contrast, the silicon and the refractory metal cannot react and the refractory metal accordingly remains in an un-reacted state in the oxide-remained region or the spacer formed region. Subsequently, the refractory metal that remain is removed using sulfuric acid.
This conventional selective silicide film forming process causes several problems in fabricating a semiconductor devices. First, where the device is deigned so that all the active regions of the logic circuit forming region B may have larger sizes than those of the DRAM cell forming region A, there is no problem. However, where the device is deigned so that part of the active regions (for example, which are used just as an active region between the gates regardless of the formation of contact) of the logic circuit forming region B may partly have smaller sizes than those of the DRAM cell forming region A, there is a problem that silicide film is defectively formed in such part. In order to solve such problems, before the silicide forming process is performed, a photolithography process should additionally be performed so that any remained oxide film in the logic circuit forming region B may entirely be removed. Where this is done, the entire process becomes very complicated and expensive.
Second, as DRAMs have been scaled down in size, capacitors of the DRAM cell, in the case of MDL, show a tendency to have a stack structure. Accordingly, a region in which a logic circuit is to be formed in a following process inevitably requires an additional deep contact forming process. In this case, since the contact hole to be formed is too deep, it is difficult to form the deep contact in the logic side just with the target etching process. Accordingly, PE-SiON film, which is an etch stopper, is needed. However, if PE-SiON deposition is added to the underlying structure shown in FIG. 1d, although there is no problem in forming contact holes in the logic side, the etching processes become very complicated in forming direct contact (DC) or buried contact (BC) in the DRAM side due to multiple layered films (for example, nitride film for SBL/oxide film for SBL/PE-SiON film for etch stopper) having etching rates different from each other that are remained in an active region. Moreover, since the amount of the remained oxide film 20 is not regular every gate spaces, a not-open phenomenon may occur while DC or BC is formed. Accordingly, the currently MDL forming process cannot employ the etch stopper film.
Accordingly, it is an object of the present invention to provide a method of selectively forming a silicide film of MDL by which an active region in a logic circuit side can be entirely covered with silicide film by employing an organic anti-reflective coating (ARC) having an excellent planarization characteristic without an additional photolithography process, even if space between gates is somewhat narrower in one or more regions, including the logic circuit forming region, than in a DRAM forming region.
It is another object of the present invention to provide a method of selectively forming a silicide film of MDL by which an etch stopper film of SiON material that is used to secure a contact hole having a high aspect ratio can be applied to a process for forming a MDL having a dual gate.
In order to achieve the objects, a method of selectively forming silicide film of MDL is provided. In accordance with the method, gates are formed provided with an insulating spacer in each of the DRAM forming region and the logic circuit forming region on a substrate. A high concentration of impurities is ion implanted selectively to form source/drain regions into only the logic circuit forming region on the substrate. A first oxide film for SBL and a nitride film for SBL are deposited in order on the resultant material. The nitride film for SBL is coated with a predetermined film having a constant thickness. An insulating film is formed in the logic circuit forming region on the predetermined film. The predetermined film that is not masked by the insulating film in the DRAM cell forming region is removed. A second oxide film for SBL is deposited on the resultant material. The second oxide film is etched back so that in the active regions between the gates of the DRAM cell forming region, the second oxide film for SBL that has a lower step coverage than the gate remains, and in the logic circuit forming region, the predetermined film is exposed. The residual predetermined film in the logic circuit forming region is removed. The nitride film for SBL and the first oxide film for SBL exclusive of the active region of the DRAM cell forming region in which the second oxide film for SBL remains are etched in order so that the gate surface of the DRAM cell forming region, the gate surface and the surface of the active region in the logic circuit forming region are exposed. A silicide film is formed on each of the gate and the active region, the surfaces of which are exposed.
It is desirable that the first oxide for SBL be formed of a medium temperature oxide material, and that the second oxide film for SBL be formed of USG material, and that the predetermined film be formed of an organic ARC having a thickness of 300 to 4000 xc3x85.
The second oxide film for SBL that remains in the active region of the DRAM cell forming region may be removed together when the first oxide film for SBL is etched for the formation of the deep contact of the logic circuit side.
In the event that the silicide film is formed as described above, since the predetermined film that fills the gap between the gates is regular in its thickness without regard to whether the active region is narrow or broad, all of the surfaces of the active region and the gate in the logic circuit forming region can be opened through the processes of removing the predetermined film and the first and second oxide films for SBL that are performed after the deposition of the oxide film of USG material and the etch back process thereto, thereby preventing the defect that the silicide film is partly not formed in the active region of the logic forming region.
Furthermore, if the second oxide film for SBL that remains in the active region of the DRAM cell forming region is just removed together when the first oxide film is etched, there is no problem even though the etch stopper film of SiON material is applied to the formation of the deep contact because it is performed at the state that any oxide films of the DRAM cell forming region and the logic circuit forming region be removed.